LTC4257
17
4257fb
APPLICATIO S I FOR ATIO
U
U
U
Layout
The LTC4257 is relativity immune to layout problems.
Excessive parasitic capacitance on the R
CLASS
pin should
be avoided. If using the DD package, include an electrically
isolated heat sink to which the exposed pad on the bottom
of the package can be soldered. For optimal thermal
performance, make the heat sink as large as possible.
Voltages in a PD can be as large as 57V, so high voltage
layout techniques should be employed.
The load capacitor connected between Pins 5 and 8 of the
LTC4257 can store significant energy when fully charged.
The design of a PD must ensure that this energy is not
inadvertently dissipated in the LTC4257. The polarity-
protection diode(s) prevent an accidental short on the
cable from causing damage. However, if the V
IN
pin is
shorted to the GND pin inside the PD while the load
capacitor is charged, current will flow through the para-
sitic body diode of the internal MOSFET and may cause
permanent damage to the LTC4257.
Input Surge Suppression
The LTC4257 is specified to operate with an absolute
maximum voltage of 100V and is designed to tolerate
brief overvoltage events. However, the pins that interface
to the outside world (primarily V
IN
and GND) can routinely
see peak voltages in excess of 10kV. To protect the
LTC4257, it is highly recommended that a transient volt-
age suppressor be installed between the bridge and the
LTC4257 (D3 in Figure 2).
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